export_equivalent_circuit#

Q3d.export_equivalent_circuit(output_file, setup=None, sweep=None, variations=None, matrix=None, cells=2, user_changed_settings=True, include_cap=True, include_cond=True, include_dcr=False, include_dcl=False, include_acr=False, include_acl=False, include_r=True, include_l=True, add_resistance=False, parse_pin_names=False, export_distributed=True, lumped_length='1meter', rise_time_value=None, rise_time_unit=None, coupling_limit_type=None, cap_limit=None, ind_limit=None, res_limit=None, cond_limit=None, model=None, frequency=0, file_type='HSPICE', include_cpp=False)#

Export matrix data.

Parameters:

output_filestr: Full path for saving the matrix data to. Options for file extensions are CIR, SML, SP, PKG, SPC, LIB, CKT, BSP, DML, and ICM.
setupstr, optional: Setup name. The default value is None, in which case the first analysis setup is used.
sweepstr, optional: Solution frequency. The default is None, in which case the default adaptive is used.
variationslist or str, optional: Design variation. The default is None, in which case the current nominal variation is used. If you provide a design variation, use the format {Name}:{Value}.
matrixstr, optional: Name of the matrix to show. The default is "Original".
cellsint, optional: Number of cells in export. Default value is 2.
user_changed_settingsbool, optional: Whether user has changed settings or not, defaulted to True. Default value is False.
include_capbool, optional: Include Capacitance. Default value is True.
include_condbool, optional: Include Conductance. Default value is True.
coupling_limit_typeint, optional: Coupling limit types. Values can be: "By Value" -> 0 or "By Fraction Of Self Term" -> 1. If None, no coupling limits are set. Default value is None.
include_dcrbool, optional: Flag indicates whether to export DC resistance matrix. Default value is False.
include_dclbool, optional: Flag indicates whether to export DC Inductance matrix. Default value is False.
include_acrbool, optional: Flag indicates whether to export AC resistance matrix. Default value is False.
include_aclbool, optional: Flag indicates whether to export AC inductance matrix. Default value is False.
include_rbool, optional: Flag indicates whether to export resistance. Default value is True.
include_lbool, optional: Flag indicates whether to export inductance. Default value is True.
add_resistancebool, optional: Adds the DC and AC resistance. Default value is True.
parse_pin_namesbool, optional: Parse pin names. Default value is False.
export_distributedbool, optional: Flag to tell whether to export in distributed mode or Lumped mode. Default value is True.
lumped_lengthstr, optional: Length of the design. Default value is 1 meter.
rise_time_valuestr, optional: Rise time to calculate the number of cells. Default value is 1e-09.
rise_time_unitstr, optional: Rise time unit. Default is s.
cap_limitstr, optional: Capacitance limit. Default value is 1pF if coupling_limit_type is 0. Default value is 0.01 if coupling_limit_type is 1.
cond_limitstr, optional: Conductance limit. Default value is 1mSie if coupling_limit_type is 0. Default value is 0.01 if coupling_limit_type is 1.
res_limitstr, optional: Resistance limit. Default value is 1ohm if coupling_limit_type is 0. Default value is 0.01 if coupling_limit_type is 1.
ind_limitstr, optional: Inductance limit. Default value is 1nH if coupling_limit_type is 0. Default value is 0.01 if coupling_limit_type is 1.
modelstr, optional: Model name or name of the sub circuit (Optional). If None then file_name is considered as model name.
frequencystr, optional: Sweep frequency in Hz. Default value is 0.
file_typestr, optional: The type of file format. Type of HSPICE file format. (All HSPICE file formats have the same extension, which is *.sp.) Options are: “Hspice”: simple HSPICE file format. “Welement”: Nexxim/HSPICE W Element file format “RLGC”: Nexxim/HSPICE RLGC W Element file format Default value is Hspice.
include_cppbool, optional: Whether to include chip package control. Default value is False.

Returns:

bool: True when successful, False when failed.

References

>>> oModule.ExportCircuit

Examples

>>> from ansys.aedt.core import Q3d
>>> aedtapp = Q3d()
>>> box = aedtapp.modeler.create_box([30, 30, 30],[10, 10, 10],name="mybox")
>>> net = aedtapp.assign_net(box,"my_net")
>>> source = aedtapp.assign_source_to_objectface(box.bottom_face_z.id, axisdir=0,
...     source_name="Source1", net_name=net.name)
>>> sink = aedtapp.assign_sink_to_objectface(box.top_face_z.id,direction=0,name="Sink1",net_name=net.name)
>>> aedtapp["d"] = "20mm"
>>> aedtapp.modeler.duplicate_along_line(objid="Box1",vector=[0, "d", 0])
>>> mysetup = aedtapp.create_setup()
>>> aedtapp.analyze_setup(mysetup.name)
>>> aedtapp.export_equivalent_circuit(output_file="test_export_circuit.cir",
...                                   setup=mysetup.name,sweep="LastAdaptive", variations=["d: 20mm"])