ExportToAedt#
- class ansys.aedt.core.filtersolutions_core.export_to_aedt.ExportToAedt#
Defines attributes and parameters for exporting filter .
This class allows you to define and modify the parameters for exporting a designed filter to
AEDT.Methods
ExportToAedt.define_export_to_desktop_distributed_dll_functions()Define C++ API DLL functions for distributed filter.
ExportToAedt.export_design([export_format, ...])Export the design directly to
AEDTor generate aPythonscript for exporting.Import tuned variables and export back over the port tuning project.
Imported
AEDTtuned parameter variables back into theFilterSolutionsproject.Import tuned variables from the port tuning project.
Load
Modelithicsmodels fromAEDT.Add a specified
Modelithicscapacitor family to the capacitor family list.Get the name of
Modelithicscapacitor family from the capacitor family list based on the specified index.Get the name of the
Modelithicscapacitor family model from the loaded list based on the specified index.Remove a specified
Modelithicscapacitor family from the capacitor family list.Add a specified
Modelithicsinductor family to the inductor family list.Get the name of
Modelithicsinductor family from the inductor family list based on the specified index.ExportToAedt.modelithics_inductor_list(row_index)Get the name of the
Modelithicsinductor family model from the loaded list based on the specified index.Remove a specified
Modelithicsinductor family from the inductor family list.Add a specified
Modelithicsresistor family to the resistor family list.Get the name of
Modelithicsresistor family from the resistor family list based on the specified index.ExportToAedt.modelithics_resistor_list(row_index)Get the name of the
Modelithicsresistor family model from the loaded list based on the specified index.Remove a specified
Modelithicsresistor family from the resistor family list.Simulate the
HFSS DesignorHFSS 3D Layout Designof the port tuning project.Simulate the port tuning project and the linked circuits schematic.
Simulate only the linked circuits schematic of the port tuning project.
Update interconnect inductor and capacitor tolerances with entered values
Update interconnect geometry equations with entered and selected parameters
Attributes
Flag indicating if the report format in dB in the exported filter to
AEDTis enabled.Flag indicating if the export with tuning port format is enabled.
Flag indicating if the parameter equations are used to define layout geometries for tuning and optimizating purpose in
HFSS.Flag indicating if the forward transfer gain report will be created upon export to
AEDT.Flag indicating if the group delay report will be created upon export to
AEDT.Flag indicating if the total voltage gain report will be created upon export to
AEDT.Flag indicating if the input return loss report will be created upon export to
AEDT.Flag indicating if the output return loss report will be created upon export to
AEDT.Flag indicating if the reverse transfer gain report will be created upon export to
AEDT.Flag indicating if the voltage gain insertion report will be created upon export to
AEDT.Flag indicating if the voltage gain source load report will be created upon export to
AEDT.Flag indicating if the filter is inserted as an
AEDT Circuit Design.Flag indicating if the filter is inserted as an
AEDT HFSS 3D Layout Design.Flag indicating if the filter is inserted as an
AEDT HFSS Design.Tolerance value of interconnect capacitor in
%.Flag indicating if the interconnect geometry optimization is enabled.
Tolerance value of interconnect inductor in
%.Length to width ratio of interconnect line.
Interconnect physical length value.
Line width to termination width ratio of interconnect line.
Interconnect conductor width value.
Maximum length to width ratio of interconnect line.
Maximum value of interconnect physical length.
ExportToAedt.interconnect_maximum_line_to_termination_width_ratioMaximum line width to termination width ratio of interconnect line.
Maximum value of interconnect conductor width.
Minimum length to width ratio of interconnect line.
Minimum value of interconnect physical length.
ExportToAedt.interconnect_minimum_line_to_termination_width_ratioMinimum line width to termination width ratio of interconnect line.
Minimum value of interconnect conductor width.
Total count of
Modelithicsfamily capacitors added to the capacitor family list.Total count of
Modelithicscapacitor families that have been loaded into the current design.Selected
Modelithicscapacitor family from the loaded list.Flag indicating if the inclusion of interconnects is enabled for
Modelithicsexport.Total count of
Modelithicsfamily inductors added to the inductor family list.Total count of
Modelithicsinductor families that have been loaded into the current design.Selected
Modelithicsinductor family from the loaded list.Total count of
Modelithicsfamily resistors added to the resistor family list.Total count of
Modelithicsresistor families that have been loaded into the current design.Selected
Modelithicsresistor family from the loaded list.Flag indicating if the optimitric parameters in the exported filter to
AEDTis enabled.Flag indicating if the optimization after exporting to
AEDTis enabled.Part libraries selection.
Flag indicating if the polar report format in the exported filter to
AEDTis enabled.Flag indicating if the ports are always placed on the side walls.
Flag indicating if the rectangular report format in the
Flag indicating if the layout is mirrored along the x-axis.
Flag indicating if the layout is mirrored along the y-axis.
Name of the exported schematic in
AEDT, displayed as the project and design names.Flag indicating if the simulation will be initiated upon export to
AEDT.Flag indicating if the
Smith Chartreport format in theSubstrate's conductor thickness.
Substrate's cover height for microstrip, suspend, and inverted substrate types.
Flag indicating if the substrate cover height is enabled.
Substrate's dielectric height.
Substrate's relative permittivity
Er.Substrate's loss tangent.
Substrate's resistivity.
Substrate's suspend dielectric height above ground plane for suspend and inverted substrate types.
Substrate type of the filter.
Substrate's lower dielectric height for unbalanced stripline substrate type.
Flag indicating if the substrate unbalanced stripline is enabled.
Flag indicating if the table data format in the exported filter to
AEDTis enabled.Flag indicating if horizontal ports are used for series element only cases.