create_edge_port#

Hfss3dLayout.create_edge_port(assignment: str | Line3dLayout, edge_number: int, is_circuit_port: bool = False, is_wave_port: bool = False, wave_horizontal_extension: float = 5, wave_vertical_extension: float = 3, wave_launcher: str = '1mm', reference_primitive: str = None, reference_edge_number: str | int = 0) → BoundaryObject3dLayout | bool[source]#

Create an edge port.

Parameters:

assignmentstr or ansys.aedt.core.modeler.pcb.object_3d_layout.Line3dLayout: Name of the primitive to create the edge port on.
edge_number: Edge number to create the edge port on.
is_circuit_portbool, optional: Whether the edge port is a circuit port. The default is False.
is_wave_portbool, optional: Whether the edge port is a wave port. The default is False.
wave_horizontal_extensionfloat, optional: Horizontal port extension factor. The default is 5.
wave_vertical_extensionfloat, optional: Vertical port extension factor. The default is 5.
wave_launcherstr, optional: PEC (perfect electrical conductor) launcher size with units. The default is “1mm”.
reference_primitivestr, optional: Name of the reference primitive to place negative edge port terminal. The default is None.
reference_edge_numberstr, int: Edge number of reference primitive. The default is 0.

Returns:

ansys.aedt.core.modules.boundary.BoundaryObject3dLayout: Port objcet port when successful, False when failed.

References

>>> oEditor.CreateEdgePort