assign_voltage_frequency_dependent_excitation_to_ports#

Circuit.assign_voltage_frequency_dependent_excitation_to_ports(ports, input_file)[source]#

Assign a frequency dependent excitation to circuit ports from a frequency dependent source (FDS format).

Parameters:
portslist

List of circuit ports to assign to the frequency dependent excitation.

input_filestr

Path to the frequency dependent file.

Returns:
ansys.aedt.core.modules.boundary.Source

Circuit Source Object.

References

>>> oDesign.UpdateSources