.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "examples\07-Circuit\Virtual_Compliance.py"
.. LINE NUMBERS ARE GIVEN BELOW.

.. only:: html

    .. note::
        :class: sphx-glr-download-link-note

        :ref:`Go to the end <sphx_glr_download_examples_07-Circuit_Virtual_Compliance.py>`
        to download the full example code.

.. rst-class:: sphx-glr-example-title

.. _sphx_glr_examples_07-Circuit_Virtual_Compliance.py:


Circuit: PCIE virtual compliance
--------------------------------
This example shows how to generate a compliance report in PyAEDT using
the ``VirtualCompliance`` class.

.. GENERATED FROM PYTHON SOURCE LINES 9-12

Perform required imports
~~~~~~~~~~~~~~~~~~~~~~~~
Perform required imports and set paths.

.. GENERATED FROM PYTHON SOURCE LINES 12-17

.. code-block:: Python


    import os.path
    import pyaedt
    from pyaedt.generic.compliance import VirtualCompliance








.. GENERATED FROM PYTHON SOURCE LINES 18-21

Set AEDT version
~~~~~~~~~~~~~~~~
Set AEDT version.

.. GENERATED FROM PYTHON SOURCE LINES 21-24

.. code-block:: Python


    aedt_version = "2024.1"








.. GENERATED FROM PYTHON SOURCE LINES 25-31

Set non-graphical mode
~~~~~~~~~~~~~~~~~~~~~~
Set non-graphical mode.
You can set ``non_graphical`` either to ``True`` or ``False``.
The Boolean parameter ``new_thread`` defines whether to create a new instance
of AEDT or try to connect to an existing instance of it.

.. GENERATED FROM PYTHON SOURCE LINES 31-35

.. code-block:: Python


    non_graphical = True
    new_thread = True








.. GENERATED FROM PYTHON SOURCE LINES 36-39

Download example files
~~~~~~~~~~~~~~~~~~~~~~
Download the project and files needed to run the example.

.. GENERATED FROM PYTHON SOURCE LINES 39-43

.. code-block:: Python

    workdir = pyaedt.downloads.download_file('pcie_compliance')

    projectdir = os.path.join(workdir, "project")








.. GENERATED FROM PYTHON SOURCE LINES 44-47

Launch AEDT
~~~~~~~~~~~
Launch AEDT.

.. GENERATED FROM PYTHON SOURCE LINES 47-50

.. code-block:: Python


    d = pyaedt.Desktop(aedt_version, new_desktop_session=new_thread, non_graphical=non_graphical)





.. rst-class:: sphx-glr-script-out

 .. code-block:: none

    C:\actions-runner\_work\_tool\Python\3.10.9\x64\lib\subprocess.py:1072: ResourceWarning: subprocess 13260 is still running
      _warn("subprocess %s is still running" % self.pid,




.. GENERATED FROM PYTHON SOURCE LINES 51-56

Open and solve layout
~~~~~~~~~~~~~~~~~~~~~
Open the HFSS 3D Layout project and analyze it using the SIwave solver.
Before solving, this code ensures that the model is solved from DC to 70GHz and that
causality and passivity are enforced.

.. GENERATED FROM PYTHON SOURCE LINES 56-68

.. code-block:: Python


    h3d = pyaedt.Hfss3dLayout(os.path.join(projectdir, "PCIE_GEN5_only_layout.aedtz"), specified_version=241)
    h3d.remove_all_unused_definitions()
    h3d.edit_cosim_options(simulate_missing_solution=False)
    h3d.setups[0].sweeps[0].props["EnforcePassivity"] = True
    h3d.setups[0].sweeps[0].props["Sweeps"]["Data"] = 'LIN 0MHz 70GHz 0.1GHz'
    h3d.setups[0].sweeps[0].props["EnforceCausality"] = True
    h3d.setups[0].sweeps[0].update()
    h3d.analyze()
    h3d = pyaedt.Hfss3dLayout(specified_version=241)
    touchstone_path = h3d.export_touchstone()








.. GENERATED FROM PYTHON SOURCE LINES 69-73

Create LNA project
~~~~~~~~~~~~~~~~~~
Use the LNA setup to retrieve Touchstone files
and generate frequency domain reports.

.. GENERATED FROM PYTHON SOURCE LINES 73-96

.. code-block:: Python


    cir = pyaedt.Circuit(projectname=h3d.project_name, designname="Touchstone")
    status, diff_pairs, comm_pairs = cir.create_lna_schematic_from_snp(input_file=touchstone_path, start_frequency=0,
                                                                       stop_frequency=70, auto_assign_diff_pairs=True,
                                                                       separation=".", pattern=["component", "pin", "net"],
                                                                       analyze=True)

    insertion = cir.get_all_insertion_loss_list(trlist=diff_pairs,
                                                reclist=diff_pairs,
                                                tx_prefix="X1",
                                                rx_prefix="U1",
                                                math_formula="dB",
                                                net_list=["RX0", "RX1", "RX2", "RX3"]
                                                )
    return_diff = cir.get_all_return_loss_list(excitation_names=diff_pairs,
                                               excitation_name_prefix="X1",
                                               math_formula="dB",
                                               net_list=["RX0", "RX1", "RX2", "RX3"]
                                               )
    return_comm = cir.get_all_return_loss_list(excitation_names=comm_pairs,
                                               excitation_name_prefix="COMMON_X1",
                                               math_formula="dB",
                                               net_list=["RX0", "RX1", "RX2", "RX3"])







.. GENERATED FROM PYTHON SOURCE LINES 97-102

Create TDR project
~~~~~~~~~~~~~~~~~~
Create a TDR project to compute transient simulation and retrieve
the TDR measurement on a differential pair.
The original circuit schematic is duplicated and modified to achieve this target.

.. GENERATED FROM PYTHON SOURCE LINES 102-111

.. code-block:: Python


    result, tdr_probe_name = cir.create_tdr_schematic_from_snp(input_file=touchstone_path,
                                                               probe_pins=["X1.A2.PCIe_Gen4_RX0_P"],
                                                               probe_ref_pins=["X1.A3.PCIe_Gen4_RX0_N"],
                                                               termination_pins=["U1.AP26.PCIe_Gen4_RX0_P",
                                                                                 "U1.AN26.PCIe_Gen4_RX0_N"],
                                                               differential=True, rise_time=35, use_convolution=True,
                                                               analyze=True, design_name="TDR")








.. GENERATED FROM PYTHON SOURCE LINES 112-116

Create AMI project
~~~~~~~~~~~~~~~~~~
Create an Ibis AMI project to compute an eye diagram simulation and retrieve
eye mask violations.

.. GENERATED FROM PYTHON SOURCE LINES 116-132

.. code-block:: Python

    result, eye_curve_tx, eye_curve_rx = cir.create_ami_schematic_from_snp(input_file=touchstone_path,
                                                                           ibis_ami=os.path.join(projectdir, "models",
                                                                                                 "pcieg5_32gt.ibs"),
                                                                           component_name="Spec_Model", tx_buffer_name="1p",
                                                                           rx_buffer_name="2p",
                                                                           tx_pins=["U1.AM25.PCIe_Gen4_TX0_CAP_P"],
                                                                           tx_refs=["U1.AL25.PCIe_Gen4_TX0_CAP_N"],
                                                                           rx_pins=["X1.B2.PCIe_Gen4_TX0_P"],
                                                                           rx_refs=["X1.B3.PCIe_Gen4_TX0_N"],
                                                                           use_ibis_buffer=False, differential=True,
                                                                           bit_pattern="random_bit_count=2.5e3 random_seed=1",
                                                                           unit_interval="31.25ps", use_convolution=True,
                                                                           analyze=True, design_name="AMI")

    cir.save_project()





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True



.. GENERATED FROM PYTHON SOURCE LINES 133-149

Create virtual compliance report
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Initialize the ``VirtualCompliance`` class
and set up the main project information needed to generate the report.


.. image:: ../../_static/virtual_compliance_class.png
   :width: 400
   :alt: Virtual compliance class description.


.. image:: ../../_static/virtual_compliance_configs.png
   :width: 400
   :alt: Virtual compliance configuration files hierarchy.



.. GENERATED FROM PYTHON SOURCE LINES 149-154

.. code-block:: Python


    template = os.path.join(workdir, "pcie_gen5_templates", "main.json")

    v = VirtualCompliance(cir.desktop_class, str(template))








.. GENERATED FROM PYTHON SOURCE LINES 155-166

Customize project and design
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Define the path to the project file and the
design names to be used in each report generation.


.. image:: ../../_static/virtual_compliance_usage.png
   :width: 400
   :alt: Virtual compliance configuration usage example.



.. GENERATED FROM PYTHON SOURCE LINES 166-177

.. code-block:: Python


    v.project_file = cir.project_file
    v.reports["insertion losses"].design_name = "LNA"
    v.reports["return losses"].design_name = "LNA"
    v.reports["common mode return losses"].design_name = "LNA"
    v.reports["tdr from circuit"].design_name = "TDR"
    v.reports["eye1"].design_name = "AMI"
    v.reports["eye3"].design_name = "AMI"
    v.parameters["erl"].design_name = "LNA"
    v.specs_folder = os.path.join(workdir, 'readme_pictures')








.. GENERATED FROM PYTHON SOURCE LINES 178-182

Define trace names
~~~~~~~~~~~~~~~~~~
Change the trace name with projects and users.
Reuse the compliance template and update traces accordingly.

.. GENERATED FROM PYTHON SOURCE LINES 182-197

.. code-block:: Python



    v.reports["insertion losses"].traces = insertion

    v.reports["return losses"].traces = return_diff

    v.reports["common mode return losses"].traces = return_comm

    v.reports["eye1"].traces = eye_curve_tx
    v.reports["eye3"].traces = eye_curve_tx
    v.reports["tdr from circuit"].traces = tdr_probe_name
    v.parameters["erl"].trace_pins = [
        ["X1.A5.PCIe_Gen4_RX1_P", "X1.A6.PCIe_Gen4_RX1_N", "U1.AR25.PCIe_Gen4_RX1_P", "U1.AP25.PCIe_Gen4_RX1_N"],
        [7, 8, 18, 17]]








.. GENERATED FROM PYTHON SOURCE LINES 198-218

Generate PDF report
~~~~~~~~~~~~~~~~~~~~
Generate the reports and produce a PDF report.


.. image:: ../../_static/virtual_compliance_scattering1.png
   :width: 400
   :alt: Insertion loss output.


.. image:: ../../_static/virtual_compliance_scattering2.png
   :width: 400
   :alt: Return loss output.


.. image:: ../../_static/virtual_compliance_eye.png
   :width: 400
   :alt: Eye diagram example.



.. GENERATED FROM PYTHON SOURCE LINES 218-222

.. code-block:: Python


    v.create_compliance_report()

    d.release_desktop(True, True)




.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True




.. rst-class:: sphx-glr-timing

   **Total running time of the script:** (6 minutes 22.169 seconds)


.. _sphx_glr_download_examples_07-Circuit_Virtual_Compliance.py:

.. only:: html

  .. container:: sphx-glr-footer sphx-glr-footer-example

    .. container:: sphx-glr-download sphx-glr-download-jupyter

      :download:`Download Jupyter notebook: Virtual_Compliance.ipynb <Virtual_Compliance.ipynb>`

    .. container:: sphx-glr-download sphx-glr-download-python

      :download:`Download Python source code: Virtual_Compliance.py <Virtual_Compliance.py>`


.. only:: html

 .. rst-class:: sphx-glr-signature

    `Gallery generated by Sphinx-Gallery <https://sphinx-gallery.github.io>`_