.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "examples\01-HFSS3DLayout\Dcir_in_3DLayout.py"
.. LINE NUMBERS ARE GIVEN BELOW.
.. only:: html
.. note::
:class: sphx-glr-download-link-note
:ref:`Go to the end <sphx_glr_download_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py>`
to download the full example code.
.. rst-class:: sphx-glr-example-title
.. _sphx_glr_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py:
HFSS 3D Layout: SIwave DCIR analysis in HFSS 3D Layout
------------------------------------------------------
This example shows how you can use configure HFSS 3D Layout for SIwave DCIR
analysis.
.. GENERATED FROM PYTHON SOURCE LINES 7-12
.. code-block:: Python
import os
import tempfile
import pyaedt
.. GENERATED FROM PYTHON SOURCE LINES 13-16
Set AEDT version
~~~~~~~~~~~~~~~~
Set AEDT version.
.. GENERATED FROM PYTHON SOURCE LINES 16-19
.. code-block:: Python
aedt_version = "2024.1"
.. GENERATED FROM PYTHON SOURCE LINES 20-23
Configure EDB for DCIR analysis
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Copy example into temporary folder
.. GENERATED FROM PYTHON SOURCE LINES 23-28
.. code-block:: Python
temp_dir = tempfile.gettempdir()
dst_dir = os.path.join(temp_dir, pyaedt.generate_unique_name("pyaedt_dcir"))
os.mkdir(dst_dir)
local_path = pyaedt.downloads.download_aedb(dst_dir)
.. GENERATED FROM PYTHON SOURCE LINES 29-30
Load example board into EDB
.. GENERATED FROM PYTHON SOURCE LINES 30-33
.. code-block:: Python
appedb = pyaedt.Edb(local_path, edbversion=aedt_version)
.. GENERATED FROM PYTHON SOURCE LINES 34-35
Create pin group on VRM positive pins
.. GENERATED FROM PYTHON SOURCE LINES 35-42
.. code-block:: Python
gnd_name = "GND"
appedb.siwave.create_pin_group_on_net(
reference_designator="U3A1",
net_name="BST_V3P3_S5",
group_name="U3A1-BST_V3P3_S5")
.. rst-class:: sphx-glr-script-out
.. code-block:: none
('U3A1-BST_V3P3_S5', <pyedb.dotnet.edb_core.edb_data.sources.PinGroup object at 0x0000022638C953F0>)
.. GENERATED FROM PYTHON SOURCE LINES 43-44
Create pin group on VRM negative pins
.. GENERATED FROM PYTHON SOURCE LINES 44-50
.. code-block:: Python
appedb.siwave.create_pin_group_on_net(
reference_designator="U3A1",
net_name="GND",
group_name="U3A1-GND")
.. rst-class:: sphx-glr-script-out
.. code-block:: none
('U3A1-GND', <pyedb.dotnet.edb_core.edb_data.sources.PinGroup object at 0x0000022638C95C00>)
.. GENERATED FROM PYTHON SOURCE LINES 51-52
Create voltage source between VRM positive and negative pin groups
.. GENERATED FROM PYTHON SOURCE LINES 52-59
.. code-block:: Python
appedb.siwave.create_voltage_source_on_pin_group(
pos_pin_group_name="U3A1-BST_V3P3_S5",
neg_pin_group_name="U3A1-GND",
magnitude=3.3,
name="U3A1-BST_V3P3_S5"
)
.. rst-class:: sphx-glr-script-out
.. code-block:: none
True
.. GENERATED FROM PYTHON SOURCE LINES 60-61
Create pin group on sink component positive pins
.. GENERATED FROM PYTHON SOURCE LINES 61-67
.. code-block:: Python
appedb.siwave.create_pin_group_on_net(
reference_designator="U2A5",
net_name="V3P3_S5",
group_name="U2A5-V3P3_S5")
.. rst-class:: sphx-glr-script-out
.. code-block:: none
('U2A5-V3P3_S5', <pyedb.dotnet.edb_core.edb_data.sources.PinGroup object at 0x0000022638C940D0>)
.. GENERATED FROM PYTHON SOURCE LINES 68-69
Create pin group on sink component negative pins
.. GENERATED FROM PYTHON SOURCE LINES 69-84
.. code-block:: Python
appedb.siwave.create_pin_group_on_net(
reference_designator="U2A5",
net_name="GND",
group_name="U2A5-GND")
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# Create place current source between sink component positive and negative pin groups
appedb.siwave.create_current_source_on_pin_group(
pos_pin_group_name="U2A5-V3P3_S5",
neg_pin_group_name="U2A5-GND",
magnitude=1,
name="U2A5-V3P3_S5"
)
.. rst-class:: sphx-glr-script-out
.. code-block:: none
True
.. GENERATED FROM PYTHON SOURCE LINES 85-86
Add SIwave DCIR analysis
.. GENERATED FROM PYTHON SOURCE LINES 86-89
.. code-block:: Python
appedb.siwave.add_siwave_dc_analysis(name="my_setup")
.. rst-class:: sphx-glr-script-out
.. code-block:: none
<pyedb.dotnet.edb_core.edb_data.siwave_simulation_setup_data.SiwaveDCSimulationSetup object at 0x0000022638C948E0>
.. GENERATED FROM PYTHON SOURCE LINES 90-93
Save and close EDB
~~~~~~~~~~~~~~~~~~
Save and close EDB.
.. GENERATED FROM PYTHON SOURCE LINES 93-97
.. code-block:: Python
appedb.save_edb()
appedb.close_edb()
.. rst-class:: sphx-glr-script-out
.. code-block:: none
True
.. GENERATED FROM PYTHON SOURCE LINES 98-101
Analysis DCIR in AEDT
~~~~~~~~~~~~~~~~~~~~~
Launch AEDT and import the configured EDB and analysis DCIR
.. GENERATED FROM PYTHON SOURCE LINES 101-106
.. code-block:: Python
desktop = pyaedt.Desktop(aedt_version, non_graphical=False, new_desktop_session=True)
hfss3dl = pyaedt.Hfss3dLayout(local_path)
hfss3dl.analyze()
hfss3dl.save_project()
.. rst-class:: sphx-glr-script-out
.. code-block:: none
True
.. GENERATED FROM PYTHON SOURCE LINES 107-110
Get element data
~~~~~~~~~~~~~~~~~~~
Get current source
.. GENERATED FROM PYTHON SOURCE LINES 110-121
.. code-block:: Python
current_source = hfss3dl.get_dcir_element_data_current_source(setup="my_setup")
print(current_source)
# ~~~~~~~~~~~~~~~~~~~
# Get via information
via = hfss3dl.get_dcir_element_data_via(setup="my_setup")
print(via)
.. rst-class:: sphx-glr-script-out
.. code-block:: none
Voltage
U2A5-V3P3_S5 3.294553
X
J1-6<BOTTOM,TOP> 0.003632
J1A6-3<BOTTOM,TOP> 0.034595
J1B2-2<BOTTOM,GND> 0.007493
J1B2-2<GND,TOP> 0.007493
J2A1-4<BOTTOM,TOP> 0.026975
... ...
via_4873<GND,TOP> 0.056947
via_4874<BOTTOM,GND> 0.086106
via_4874<GND,TOP> 0.086106
via_4875<BOTTOM,GND> 0.082550
via_4875<GND,TOP> 0.082550
[883 rows x 1 columns]
.. GENERATED FROM PYTHON SOURCE LINES 122-125
Get voltage
~~~~~~~~~~~
Get voltage from dcir solution data
.. GENERATED FROM PYTHON SOURCE LINES 125-128
.. code-block:: Python
voltage = hfss3dl.get_dcir_solution_data(setup="my_setup", show="Sources", category="Voltage")
print({expression: voltage.data_magnitude(expression) for expression in voltage.expressions})
.. rst-class:: sphx-glr-script-out
.. code-block:: none
{'SeriesRV(U3A1-BST_V3P3_S5)': [1.000632290113], 'V(U2A5-V3P3_S5)': [3294.553400696]}
.. GENERATED FROM PYTHON SOURCE LINES 129-131
Close AEDT
~~~~~~~~~~
.. GENERATED FROM PYTHON SOURCE LINES 131-132
.. code-block:: Python
desktop.release_desktop()
.. rst-class:: sphx-glr-script-out
.. code-block:: none
True
.. rst-class:: sphx-glr-timing
**Total running time of the script:** (2 minutes 27.214 seconds)
.. _sphx_glr_download_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py:
.. only:: html
.. container:: sphx-glr-footer sphx-glr-footer-example
.. container:: sphx-glr-download sphx-glr-download-jupyter
:download:`Download Jupyter notebook: Dcir_in_3DLayout.ipynb <Dcir_in_3DLayout.ipynb>`
.. container:: sphx-glr-download sphx-glr-download-python
:download:`Download Python source code: Dcir_in_3DLayout.py <Dcir_in_3DLayout.py>`
.. only:: html
.. rst-class:: sphx-glr-signature
`Gallery generated by Sphinx-Gallery <https://sphinx-gallery.github.io>`_