.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "examples\01-HFSS3DLayout\Dcir_in_3DLayout.py"
.. LINE NUMBERS ARE GIVEN BELOW.

.. only:: html

    .. note::
        :class: sphx-glr-download-link-note

        :ref:`Go to the end <sphx_glr_download_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py>`
        to download the full example code

.. rst-class:: sphx-glr-example-title

.. _sphx_glr_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py:


HFSS 3D Layout: SIwave DCIR analysis in HFSS 3D Layout
------------------------------------------------------
This example shows how you can use configure HFSS 3D Layout for SIwave DCIR
analysis.

.. GENERATED FROM PYTHON SOURCE LINES 7-12

.. code-block:: default


    import os
    import tempfile
    import pyaedt








.. GENERATED FROM PYTHON SOURCE LINES 13-16

Configure EDB for DCIR analysis
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Copy example into temporary folder

.. GENERATED FROM PYTHON SOURCE LINES 16-21

.. code-block:: default

    temp_dir = tempfile.gettempdir()
    dst_dir = os.path.join(temp_dir, pyaedt.generate_unique_name("pyaedt_dcir"))
    os.mkdir(dst_dir)
    local_path = pyaedt.downloads.download_aedb(dst_dir)








.. GENERATED FROM PYTHON SOURCE LINES 22-23

Load example board into EDB

.. GENERATED FROM PYTHON SOURCE LINES 23-27

.. code-block:: default


    edbversion = "2023.2"
    appedb = pyaedt.Edb(local_path, edbversion=edbversion)








.. GENERATED FROM PYTHON SOURCE LINES 28-29

Create pin group on VRM positive pins

.. GENERATED FROM PYTHON SOURCE LINES 29-36

.. code-block:: default


    gnd_name = "GND"
    appedb.siwave.create_pin_group_on_net(
        reference_designator="U3A1",
        net_name="BST_V3P3_S5",
        group_name="U3A1-BST_V3P3_S5")





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    ('U3A1-BST_V3P3_S5', <pyaedt.edb_core.edb_data.sources.PinGroup object at 0x000001A9F8EBB4F0>)



.. GENERATED FROM PYTHON SOURCE LINES 37-38

Create pin group on VRM negative pins

.. GENERATED FROM PYTHON SOURCE LINES 38-44

.. code-block:: default


    appedb.siwave.create_pin_group_on_net(
        reference_designator="U3A1",
        net_name="GND",
        group_name="U3A1-GND")





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    ('U3A1-GND', <pyaedt.edb_core.edb_data.sources.PinGroup object at 0x000001A9F8EB9AE0>)



.. GENERATED FROM PYTHON SOURCE LINES 45-46

Create voltage source between VRM positive and negative pin groups

.. GENERATED FROM PYTHON SOURCE LINES 46-53

.. code-block:: default

    appedb.siwave.create_voltage_source_on_pin_group(
        pos_pin_group_name="U3A1-BST_V3P3_S5",
        neg_pin_group_name="U3A1-GND",
        magnitude=3.3,
        name="U3A1-BST_V3P3_S5"
    )





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True



.. GENERATED FROM PYTHON SOURCE LINES 54-55

Create pin group on sink component positive pins

.. GENERATED FROM PYTHON SOURCE LINES 55-61

.. code-block:: default


    appedb.siwave.create_pin_group_on_net(
        reference_designator="U2A5",
        net_name="V3P3_S5",
        group_name="U2A5-V3P3_S5")





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    ('U2A5-V3P3_S5', <pyaedt.edb_core.edb_data.sources.PinGroup object at 0x000001A9A80A4310>)



.. GENERATED FROM PYTHON SOURCE LINES 62-63

Create pin group on sink component negative pins

.. GENERATED FROM PYTHON SOURCE LINES 63-78

.. code-block:: default


    appedb.siwave.create_pin_group_on_net(
        reference_designator="U2A5",
        net_name="GND",
        group_name="U2A5-GND")

    # ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Create place current source between sink component positive and negative pin groups
    appedb.siwave.create_current_source_on_pin_group(
        pos_pin_group_name="U2A5-V3P3_S5",
        neg_pin_group_name="U2A5-GND",
        magnitude=1,
        name="U2A5-V3P3_S5"
    )





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True



.. GENERATED FROM PYTHON SOURCE LINES 79-80

Add SIwave DCIR analysis

.. GENERATED FROM PYTHON SOURCE LINES 80-83

.. code-block:: default


    appedb.siwave.add_siwave_dc_analysis(name="my_setup")





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    <pyaedt.edb_core.edb_data.siwave_simulation_setup_data.SiwaveDCSimulationSetup object at 0x000001A9A7EE4C10>



.. GENERATED FROM PYTHON SOURCE LINES 84-87

Save and close EDB
~~~~~~~~~~~~~~~~~~
Save and close EDB.

.. GENERATED FROM PYTHON SOURCE LINES 87-91

.. code-block:: default


    appedb.save_edb()
    appedb.close_edb()





.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True



.. GENERATED FROM PYTHON SOURCE LINES 92-95

Analysis DCIR in AEDT
~~~~~~~~~~~~~~~~~~~~~
Launch AEDT and import the configured EDB and analysis DCIR

.. GENERATED FROM PYTHON SOURCE LINES 95-100

.. code-block:: default

    desktop = pyaedt.Desktop(edbversion, non_graphical=False, new_desktop_session=True)
    hfss3dl = pyaedt.Hfss3dLayout(local_path)
    hfss3dl.analyze()
    hfss3dl.save_project()





.. rst-class:: sphx-glr-script-out

 .. code-block:: none

    Initializing new desktop!
    Returning found desktop with PID 4808!

    True



.. GENERATED FROM PYTHON SOURCE LINES 101-104

Get element data
~~~~~~~~~~~~~~~~~~~
Get loop resistance

.. GENERATED FROM PYTHON SOURCE LINES 104-121

.. code-block:: default


    loop_resistance = hfss3dl.get_dcir_element_data_loop_resistance(setup_name="my_setup")
    print(loop_resistance)

    # ~~~~~~~~~~~~~~~~~~~
    # Get current source

    current_source = hfss3dl.get_dcir_element_data_current_source(setup_name="my_setup")
    print(current_source)

    # ~~~~~~~~~~~~~~~~~~~
    # Get via information

    via = hfss3dl.get_dcir_element_data_via(setup_name="my_setup")
    print(via)






.. rst-class:: sphx-glr-script-out

 .. code-block:: none

                     U2A5-V3P3_S5 U3A1-BST_V3P3_S5
    U2A5-V3P3_S5            False         0.004444
    U3A1-BST_V3P3_S5     0.004444            False
                   Voltage
    U2A5-V3P3_S5  3.294553
                                 X
    J1-6<BOTTOM,TOP>      0.003632
    J1A6-3<BOTTOM,TOP>    0.034595
    J1B2-2<BOTTOM,GND>    0.007493
    J1B2-2<GND,TOP>       0.007493
    J2A1-4<BOTTOM,TOP>    0.026975
    ...                        ...
    via_4873<GND,TOP>     0.056947
    via_4874<BOTTOM,GND>  0.086106
    via_4874<GND,TOP>     0.086106
    via_4875<BOTTOM,GND>  0.082550
    via_4875<GND,TOP>     0.082550

    [883 rows x 1 columns]




.. GENERATED FROM PYTHON SOURCE LINES 122-125

Get voltage
~~~~~~~~~~~
Get voltage from dcir solution data

.. GENERATED FROM PYTHON SOURCE LINES 125-131

.. code-block:: default

    voltage = hfss3dl.get_dcir_solution_data(
        setup_name="my_setup",
        show="Sources",
        category="Voltage")
    print({expression: voltage.data_magnitude(expression) for  expression in voltage.expressions})





.. rst-class:: sphx-glr-script-out

 .. code-block:: none

    {'SeriesRV(U3A1-BST_V3P3_S5)': [1.000632290113], 'V(U2A5-V3P3_S5)': [3294.553400696]}




.. GENERATED FROM PYTHON SOURCE LINES 132-134

Close AEDT
~~~~~~~~~~

.. GENERATED FROM PYTHON SOURCE LINES 134-136

.. code-block:: default

    hfss3dl.close_project()
    desktop.release_desktop()




.. rst-class:: sphx-glr-script-out

 .. code-block:: none


    True




.. rst-class:: sphx-glr-timing

   **Total running time of the script:** (1 minutes 46.163 seconds)


.. _sphx_glr_download_examples_01-HFSS3DLayout_Dcir_in_3DLayout.py:

.. only:: html

  .. container:: sphx-glr-footer sphx-glr-footer-example




    .. container:: sphx-glr-download sphx-glr-download-python

      :download:`Download Python source code: Dcir_in_3DLayout.py <Dcir_in_3DLayout.py>`

    .. container:: sphx-glr-download sphx-glr-download-jupyter

      :download:`Download Jupyter notebook: Dcir_in_3DLayout.ipynb <Dcir_in_3DLayout.ipynb>`


.. only:: html

 .. rst-class:: sphx-glr-signature

    `Gallery generated by Sphinx-Gallery <https://sphinx-gallery.github.io>`_