.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples\00-EDB\13_edb_create_component.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_00-EDB_13_edb_create_component.py: EDB: geometry creation ---------------------- This example shows how to 1, Create a layout layer stackup. 2, Create Padstack definition. 3, Place padstack instances at given location. 4, Create primitives, polygon and trace. 5, Create component from pins. 6, Create HFSS simulation setup and excitation ports. .. GENERATED FROM PYTHON SOURCE LINES 13-20 Final expected project ~~~~~~~~~~~~~~~~~~~~~~ .. image:: ../../_static/connector_example.png :width: 600 :alt: Connector from Vias. ##################################################################### .. GENERATED FROM PYTHON SOURCE LINES 23-27 Create connector component from pad-stack ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Initialize an empty EDB layout object on version 2023 R2. ##################################################################### .. GENERATED FROM PYTHON SOURCE LINES 27-39 .. code-block:: default import os import pyaedt from pyaedt import Edb aedb_path = os.path.join(pyaedt.generate_unique_folder_name(), pyaedt.generate_unique_name("component_example") + ".aedb") edb = Edb(edbpath=aedb_path, edbversion="2023.2") print("EDB is located at {}".format(aedb_path)) .. rst-class:: sphx-glr-script-out .. code-block:: none EDB is located at D:\Temp\pyaedt_prj_2OT\component_example_OT78OU.aedb .. GENERATED FROM PYTHON SOURCE LINES 40-42 Initialize variables ~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 42-63 .. code-block:: default layout_count = 12 diel_material_name = "FR4_epoxy" diel_thickness = "0.15mm" cond_thickness_outer = "0.05mm" cond_thickness_inner = "0.017mm" soldermask_thickness = "0.05mm" trace_in_layer = "TOP" trace_out_layer = "L10" trace_width = "200um" connector_size = 2e-3 conectors_position = [[0, 0], [10e-3, 0]] ################ # Create stackup # ~~~~~~~~~~~~~~ edb.stackup.create_symmetric_stackup(layer_count=layout_count, inner_layer_thickness=cond_thickness_inner, outer_layer_thickness=cond_thickness_outer, soldermask_thickness=soldermask_thickness, dielectric_thickness=diel_thickness, dielectric_material=diel_material_name) .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 64-67 Create ground planes ~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 67-74 .. code-block:: default ground_layers = [layer_name for layer_name in edb.stackup.signal_layers.keys() if layer_name not in [trace_in_layer, trace_out_layer]] plane_shape = edb.modeler.Shape("rectangle", pointA=["-3mm", "-3mm"], pointB=["13mm", "3mm"]) for i in ground_layers: edb.modeler.create_polygon(plane_shape, i, net_name="VSS") .. GENERATED FROM PYTHON SOURCE LINES 75-77 Add design variables ~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 77-84 .. code-block:: default edb.add_design_variable("$via_hole_size", "0.3mm") edb.add_design_variable("$antipaddiam", "0.7mm") edb.add_design_variable("$paddiam", "0.5mm") edb.add_design_variable("trace_in_width", "0.2mm", is_parameter=True) edb.add_design_variable("trace_out_width", "0.1mm", is_parameter=True) .. rst-class:: sphx-glr-script-out .. code-block:: none (True, ) .. GENERATED FROM PYTHON SOURCE LINES 85-87 Create padstack definition ~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 87-91 .. code-block:: default edb.padstacks.create_padstack(padstackname="Via", holediam="$via_hole_size", antipaddiam="$antipaddiam", paddiam="$paddiam") .. rst-class:: sphx-glr-script-out .. code-block:: none 'Via' .. GENERATED FROM PYTHON SOURCE LINES 92-94 Create connector 1 ~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 94-110 .. code-block:: default component1_pins = [edb.padstacks.place_padstack(conectors_position[0], "Via", net_name="VDD", fromlayer=trace_in_layer, tolayer=trace_out_layer), edb.padstacks.place_padstack([conectors_position[0][0] - connector_size / 2, conectors_position[0][1] - connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[0][0] + connector_size / 2, conectors_position[0][1] - connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[0][0] + connector_size / 2, conectors_position[0][1] + connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[0][0] - connector_size / 2, conectors_position[0][1] + connector_size / 2], "Via", net_name="VSS")] .. GENERATED FROM PYTHON SOURCE LINES 111-113 Create connector 2 ~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 113-130 .. code-block:: default component2_pins = [ edb.padstacks.place_padstack(conectors_position[-1], "Via", net_name="VDD", fromlayer=trace_in_layer, tolayer=trace_out_layer), edb.padstacks.place_padstack([conectors_position[1][0] - connector_size / 2, conectors_position[1][1] - connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[1][0] + connector_size / 2, conectors_position[1][1] - connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[1][0] + connector_size / 2, conectors_position[1][1] + connector_size / 2], "Via", net_name="VSS"), edb.padstacks.place_padstack([conectors_position[1][0] - connector_size / 2, conectors_position[1][1] + connector_size / 2], "Via", net_name="VSS")] .. GENERATED FROM PYTHON SOURCE LINES 131-133 Create layout pins ~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 133-137 .. code-block:: default for padstack_instance in list(edb.padstacks.instances.values()): padstack_instance.is_pin = True .. GENERATED FROM PYTHON SOURCE LINES 138-140 create component from pins ~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 140-144 .. code-block:: default edb.components.create(component1_pins, 'connector_1') edb.components.create(component2_pins, 'connector_2') .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 145-147 Creating ports and adding simulation setup using SimulationConfiguration class ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 147-160 .. code-block:: default sim_setup = edb.new_simulation_configuration() sim_setup.solver_type = sim_setup.SOLVER_TYPE.Hfss3dLayout sim_setup.batch_solve_settings.cutout_subdesign_expansion = 0.01 sim_setup.batch_solve_settings.do_cutout_subdesign = False sim_setup.batch_solve_settings.signal_nets = ["VDD"] sim_setup.batch_solve_settings.components = ["connector_1", "connector_2"] sim_setup.batch_solve_settings.power_nets = ["VSS"] sim_setup.ac_settings.start_freq = "0GHz" sim_setup.ac_settings.stop_freq = "5GHz" sim_setup.ac_settings.step_freq = "1GHz" edb.build_simulation_project(sim_setup) .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 161-163 Save EDB and open in AEDT ~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 163-171 .. code-block:: default edb.save_edb() edb.close_edb() h3d = pyaedt.Hfss3dLayout(specified_version="2023.2", projectname=aedb_path, non_graphical=False, new_desktop_session=True) h3d.release_desktop(False, False) .. rst-class:: sphx-glr-script-out .. code-block:: none Initializing new desktop! True .. rst-class:: sphx-glr-timing **Total running time of the script:** (0 minutes 46.177 seconds) .. _sphx_glr_download_examples_00-EDB_13_edb_create_component.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: 13_edb_create_component.py <13_edb_create_component.py>` .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: 13_edb_create_component.ipynb <13_edb_create_component.ipynb>` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_