.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples\00-EDB\01_edb_example.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_00-EDB_01_edb_example.py: EDB: Siwave analysis from EDB setup ----------------------------------- This example shows how you can use EDB to interact with a layout. .. GENERATED FROM PYTHON SOURCE LINES 7-10 Perform required imports ~~~~~~~~~~~~~~~~~~~~~~~~ Perform required imports. .. GENERATED FROM PYTHON SOURCE LINES 10-23 .. code-block:: default import os import time import pyaedt temp_folder = pyaedt.generate_unique_folder_name() targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) siwave_file = os.path.join(os.path.dirname(targetfile), "ANSYS-HSD_V1.siw") print(targetfile) aedt_file = targetfile[:-4] + "aedt" .. rst-class:: sphx-glr-script-out .. code-block:: none D:\Temp\pyaedt_prj_JOW\edb/ANSYS-HSD_V1.aedb .. GENERATED FROM PYTHON SOURCE LINES 24-27 Launch EDB ~~~~~~~~~~ Launch the :class:`pyaedt.Edb` class, using EDB 2023 R2 and SI units. .. GENERATED FROM PYTHON SOURCE LINES 27-32 .. code-block:: default edb_version = "2023.2" if os.path.exists(aedt_file): os.remove(aedt_file) edb = pyaedt.Edb(edbpath=targetfile, edbversion=edb_version) .. GENERATED FROM PYTHON SOURCE LINES 33-37 Compute nets and components ~~~~~~~~~~~~~~~~~~~~~~~~~~~ Computes nets and components. There are queries for nets, stackups, layers, components, and geometries. .. GENERATED FROM PYTHON SOURCE LINES 37-43 .. code-block:: default print("Nets {}".format(len(edb.nets.netlist))) start = time.time() print("Components {}".format(len(edb.components.components.keys()))) print("elapsed time = ", time.time() - start) .. rst-class:: sphx-glr-script-out .. code-block:: none Nets 348 Components 509 elapsed time = 0.0 .. GENERATED FROM PYTHON SOURCE LINES 44-50 Get pin position ~~~~~~~~~~~~~~~~ Get the position for a specific pin. The next section shows how to get all pins for a specific component and the positions of each of them. Each pin is a list of ``[X, Y]`` coordinate positions. .. GENERATED FROM PYTHON SOURCE LINES 50-55 .. code-block:: default pins = edb.components["U2"].pins for pin in edb.components["U2"].pins.values(): print(pin.position) .. rst-class:: sphx-glr-script-out .. code-block:: none [0.13149999608000001, 0.018999997560000016] [0.13099999708, 0.018999997560000016] [0.13049999808, 0.018999997560000013] [0.12999999654000002, 0.01899999756000001] [0.12949999754000002, 0.01899999756000001] [0.12899999854000002, 0.01899999756000001] [0.12849999700000003, 0.018999997560000006] [0.12799999800000003, 0.018999997560000002] [0.12749999646000001, 0.018999997560000002] [0.12699999746, 0.018999997560000002] [0.12649999846, 0.01899999756] [0.12599999692000002, 0.018999997559999995] [0.12549999792000002, 0.018999997559999995] [0.12499999638000002, 0.018999997559999995] [0.12449999738000002, 0.018999997559999992] [0.12399999838000002, 0.01899999755999999] [0.12349999684000001, 0.01899999755999999] [0.12299999784000001, 0.01899999755999999] [0.12234999660000001, 0.019649998799999985] [0.12234999660000001, 0.020149997799999986] [0.12234999660000001, 0.020649996799999987] [0.12234999660000001, 0.021149998339999986] [0.12234999660000001, 0.021649997339999984] [0.12234999660000001, 0.022149996339999985] [0.12234999660000001, 0.022649997879999984] [0.12234999660000001, 0.023149996879999985] [0.1223499966, 0.023649998419999985] [0.1223499966, 0.024149997419999986] [0.1223499966, 0.024649996419999987] [0.1223499966, 0.025149997959999986] [0.1223499966, 0.025649996959999984] [0.1223499966, 0.026149998499999987] [0.1223499966, 0.026649997499999984] [0.1223499966, 0.027149996499999985] [0.12234999659999998, 0.027649998039999985] [0.12234999659999998, 0.028149997039999985] [0.12234999659999998, 0.028649998579999985] [0.12234999659999998, 0.029149997579999982] [0.12299999783999999, 0.029799998819999986] [0.12349999683999999, 0.02979999881999999] [0.12399999837999998, 0.029799998819999993] [0.12449999737999998, 0.029799998819999993] [0.12499999637999998, 0.029799998819999993] [0.12549999792, 0.029799998819999996] [0.12599999691999997, 0.02979999882] [0.12649999845999998, 0.02979999882] [0.12699999745999999, 0.02979999882] [0.12749999646, 0.029799998820000003] [0.12799999799999998, 0.029799998820000007] [0.12849999699999998, 0.029799998820000007] [0.12899999854, 0.029799998820000007] [0.12949999754, 0.02979999882000001] [0.12999999653999997, 0.029799998820000013] [0.13049999807999998, 0.029799998820000013] [0.13099999707999999, 0.029799998820000013] [0.13149999608, 0.029799998820000017] [0.13214999732, 0.029149997580000017] [0.13214999732, 0.02864999858000002] [0.13214999732, 0.02814999704000002] [0.13214999732, 0.02764999804000002] [0.13214999732, 0.02714999650000002] [0.13214999732, 0.02664999750000002] [0.13214999732, 0.026149998500000018] [0.13214999732, 0.02564999696000002] [0.13214999732, 0.02514999796000002] [0.13214999732, 0.024649996420000018] [0.13214999732, 0.02414999742000002] [0.13214999732, 0.02364999842000002] [0.13214999732000002, 0.02314999688000002] [0.13214999732000002, 0.02264999788000002] [0.13214999732000002, 0.02214999634000002] [0.13214999732000002, 0.02164999734000002] [0.13214999732000002, 0.021149998340000017] [0.13214999732000002, 0.020649996800000018] [0.13214999732000002, 0.02014999780000002] [0.13214999732000002, 0.01964999880000002] [0.12704999736, 0.02737999604] .. GENERATED FROM PYTHON SOURCE LINES 56-59 Get all nets connected to a component ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Get all nets connected to a specific component. .. GENERATED FROM PYTHON SOURCE LINES 59-62 .. code-block:: default edb.components.get_component_net_connection_info("U2") .. rst-class:: sphx-glr-script-out .. code-block:: none {'refdes': ['U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2'], 'pin_name': ['1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '20', '21', '22', '23', '24', '25', '26', '27', '28', '29', '30', '31', '32', '33', '34', '35', '36', '37', '38', '39', '40', '41', '42', '43', '44', '45', '46', '47', '48', '49', '50', '51', '52', '53', '54', '55', '56', '57', '58', '59', '60', '61', '62', '63', '64', '65', '66', '67', '68', '69', '70', '71', '72', '73', '74', '75', '76', '77'], 'net_name': ['', '', '', '', '', '', '', '', '', '', '', '', '', '', '', '', '', '', '', '1V0', '1V0', '1V0', '1V0', '1V0', '1V0', '1V0', '1V0', '1V0', '', '', '', 'GND', 'GND', 'GND', 'GND', 'GND', 'GND', 'GND', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '5V', '', '', 'NetC10_2', 'NetC10_1', '', '', 'NetR12_1', '', '5V', 'GND', '', '1V0', '', 'NetC9_2', 'NetR8_1', '', 'NetR13_1', 'NetR11_2', '', '', '', '', '', '', '', 'GND']} .. GENERATED FROM PYTHON SOURCE LINES 63-66 Compute rats ~~~~~~~~~~~~ Computes rats. .. GENERATED FROM PYTHON SOURCE LINES 66-69 .. code-block:: default rats = edb.components.get_rats() .. GENERATED FROM PYTHON SOURCE LINES 70-75 Get all DC-connected net lists through inductance ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Get all DC-connected net lists through inductance. The inputs needed are ground net lists. The returned list contains all nets connected to a ground through an inductor. .. GENERATED FROM PYTHON SOURCE LINES 75-80 .. code-block:: default GROUND_NETS = ["GND", "GND_DP"] dc_connected_net_list = edb.nets.get_dcconnected_net_list(GROUND_NETS) print(dc_connected_net_list) .. rst-class:: sphx-glr-script-out .. code-block:: none [{'AVCC_1V3', 'NetD3_2'}, {'2V5', 'NetC271_1', '1.8V_DVDDH'}, {'1.2V_AVDDL', '1.2V_AVDLL_PLL', '1.2V_DVDDL'}, {'PDEN', 'SFPA_VCCR', 'USB3_VBUS', 'NetIC1_8', '5V', 'SFPA_VCCT', '3.3V_AVDDH'}, {'NetR22_1', 'VDD_DDR'}, {'NetR8_1', '1V0'}] .. GENERATED FROM PYTHON SOURCE LINES 81-84 Get power tree based on a specific net ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Get the power tree based on a specific net. .. GENERATED FROM PYTHON SOURCE LINES 84-91 .. code-block:: default VRM = "U1" OUTPUT_NET = "AVCC_1V3" powertree_df, component_list_columns, net_group = edb.nets.get_powertree(OUTPUT_NET, GROUND_NETS) for el in powertree_df: print(el) .. rst-class:: sphx-glr-script-out .. code-block:: none ['R1', '1', 'AVCC_1V3', 'Resistor', 'RESC1608X05N', '1'] ['L10', '2', 'AVCC_1V3', 'Inductor', 'WE-Coil-PD4-S', '2'] ['C46', '1', 'AVCC_1V3', 'Capacitor', 'CAPMP7343X31N', '1'] ['C53', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C68', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C52', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C45', '1', 'AVCC_1V3', 'Capacitor', 'CAPC1608X08N', '1'] ['C55', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C58', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C54', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C60', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C57', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C73', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C69', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C56', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C205', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C238', '2', 'AVCC_1V3', 'Capacitor', 'CAPC1005X33X10LL5', '2'] ['C145', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C144', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C143', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C142', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C141', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C140', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C139', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C138', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C137', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C136', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C135', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C134', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C133', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C132', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C131', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C130', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C129', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['C128', '2', 'AVCC_1V3', 'Capacitor', 'CAPC0603X33X15LL03T05', '2'] ['U1', 'D28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'D29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'F28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'F29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'H28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'H29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'K28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'K29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'M15', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'M28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'M29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'P13', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'P22', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'P24', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'P28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'P29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'T10', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'T28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'T29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'V28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'V29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'W11', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'W18', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'W19', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'Y11', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'Y28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'Y29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AB28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AB29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AD11', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AD28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AD29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AE23', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AF13', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AF23', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AF28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AF29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AG19', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AH16', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AH28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AH29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AK28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AK29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AM28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AM29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AP28', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['U1', 'AP29', 'AVCC_1V3', 'IC', 'ALTR-FBGA1517-Ansys', 'D28-D29-F28-F29-H28-H29-K28-K29-M15-M28-M29-P13-P22-P24-P28-P29-T10-T28-T29-V28-V29-W11-W18-W19-Y11-Y28-Y29-AB28-AB29-AD11-AD28-AD29-AE23-AF13-AF23-AF28-AF29-AG19-AH16-AH28-AH29-AK28-AK29-AM28-AM29-AP28-AP29'] ['L10', '1', 'NetD3_2', 'Inductor', 'WE-Coil-PD4-S', '1'] ['IC2', '1', 'NetD3_2', 'Other', 'SOIC127P-680x175-8_N', '1'] ['D3', '2', 'NetD3_2', 'Other', 'DO214AA', '2'] .. GENERATED FROM PYTHON SOURCE LINES 92-96 Delete all RLCs with only one pin ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Delete all RLCs with only one pin. This method provides a useful way of removing components not needed in the simulation. .. GENERATED FROM PYTHON SOURCE LINES 96-99 .. code-block:: default edb.components.delete_single_pin_rlc() .. rst-class:: sphx-glr-script-out .. code-block:: none [] .. GENERATED FROM PYTHON SOURCE LINES 100-103 Delete components ~~~~~~~~~~~~~~~~~ Delete manually one or more components. .. GENERATED FROM PYTHON SOURCE LINES 103-106 .. code-block:: default edb.components.delete("C380") .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 107-110 Delete nets ~~~~~~~~~~~ Delete manually one or more nets. .. GENERATED FROM PYTHON SOURCE LINES 110-113 .. code-block:: default edb.nets.delete("PDEN") .. rst-class:: sphx-glr-script-out .. code-block:: none ['PDEN'] .. GENERATED FROM PYTHON SOURCE LINES 114-117 Get stackup limits ~~~~~~~~~~~~~~~~~~ Get the stackup limits (top and bottom layers and elevations). .. GENERATED FROM PYTHON SOURCE LINES 117-122 .. code-block:: default print(edb.stackup.limits()) .. rst-class:: sphx-glr-script-out .. code-block:: none ('1_Top', 0.0017480000000000004, '16_Bottom', 0.0) .. GENERATED FROM PYTHON SOURCE LINES 123-126 Create voltage source and Siwave DCIR analysis ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Create a voltage source and then set up a DCIR analysis. .. GENERATED FROM PYTHON SOURCE LINES 126-136 .. code-block:: default edb.siwave.create_voltage_source_on_net("U1", "AVCC_1V3", "U1", "GND", 1.3, 0, "V1") edb.siwave.create_current_source_on_net("IC2", "NetD3_2", "IC2", "GND", 1.0, 0, "I1") setup = edb.siwave.add_siwave_dc_analysis("myDCIR_4") setup.use_dc_custom_settings = True setup.set_dc_slider = 0 setup.add_source_terminal_to_ground("V1", 1) .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 137-140 Save modifications ~~~~~~~~~~~~~~~~~~ Save modifications. .. GENERATED FROM PYTHON SOURCE LINES 140-146 .. code-block:: default edb.save_edb() edb.nets.plot(None, "1_Top",plot_components_on_top=True) siw_file = edb.solve_siwave() .. image-sg:: /examples/00-EDB/images/sphx_glr_01_edb_example_001.png :alt: main :srcset: /examples/00-EDB/images/sphx_glr_01_edb_example_001.png :class: sphx-glr-single-img .. GENERATED FROM PYTHON SOURCE LINES 147-150 Export Siwave Reports ~~~~~~~~~~~~~~~~~~~~~ Export all DC Reports quantities. .. GENERATED FROM PYTHON SOURCE LINES 150-152 .. code-block:: default outputs = edb.export_siwave_dc_results(siw_file, setup.name, ) .. rst-class:: sphx-glr-script-out .. code-block:: none ['"C:\\Program Files\\AnsysEM\\v232\\Win64\\siwave.exe"', '-embedding', '-RunScriptAndExit', '"D:\\Temp\\pyaedt_prj_JOW\\edb\\export_results.py"'] .. GENERATED FROM PYTHON SOURCE LINES 153-156 Close EDB ~~~~~~~~~ Close EDB. After EDB is closed, it can be opened by AEDT. .. GENERATED FROM PYTHON SOURCE LINES 156-159 .. code-block:: default edb.close_edb() .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 160-163 Postprocess in Siwave ~~~~~~~~~~~~~~~~~~~~~ Open Siwave and generate a report. This works on Window only. .. GENERATED FROM PYTHON SOURCE LINES 163-172 .. code-block:: default # from pyaedt import Siwave # siwave = Siwave("2023.2") # siwave.open_project(siwave_file) # report_file = os.path.join(temp_folder,'Ansys.htm') # # siwave.export_siwave_report("myDCIR_4", report_file) # siwave.close_project() # siwave.quit_application() .. rst-class:: sphx-glr-timing **Total running time of the script:** (1 minutes 24.155 seconds) .. _sphx_glr_download_examples_00-EDB_01_edb_example.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: 01_edb_example.py <01_edb_example.py>` .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: 01_edb_example.ipynb <01_edb_example.ipynb>` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_