.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples\00-EDB\12_edb_sma_connector_on_board.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_00-EDB_12_edb_sma_connector_on_board.py: EDB: geometry creation ---------------------- This example shows how to 1, Create a parameterized PCB layout design. 2, Place 3D component on PCB. 3, Create HFSS setup and frequency sweep with a mesh operation. 4, Create return loss plot .. GENERATED FROM PYTHON SOURCE LINES 11-18 Final expected project ~~~~~~~~~~~~~~~~~~~~~~ .. image:: ../../_static/edb_example_12_sma_connector_on_board.png :width: 600 :alt: Differential Vias. ##################################################################### .. GENERATED FROM PYTHON SOURCE LINES 21-25 Create parameterized PCB ~~~~~~~~~~~~~~~~~~~~~~~~ Initialize an empty EDB layout object on version 2023 R2. ##################################################################### .. GENERATED FROM PYTHON SOURCE LINES 25-36 .. code-block:: default import os import numpy as np import pyaedt ansys_version = "2023.2" aedb_path = os.path.join(pyaedt.generate_unique_folder_name(), pyaedt.generate_unique_name("pcb") + ".aedb") edb = pyaedt.Edb(edbpath=aedb_path, edbversion=ansys_version) print("EDB is located at {}".format(aedb_path)) .. rst-class:: sphx-glr-script-out .. code-block:: none EDB is located at D:\Temp\pyaedt_prj_MBU\pcb_DBA6Q7.aedb .. GENERATED FROM PYTHON SOURCE LINES 37-39 Create FR4 material ~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 39-61 .. code-block:: default edb.materials.add_dielectric_material("ANSYS_FR4", 3.5, 0.005) ################ # Create stackup # ~~~~~~~~~~~~~~ # A stackup can be created by importing from a csv/xml file or adding layer by layer. # edb.add_design_variable("$DIEL_T", "0.15mm") edb.stackup.add_layer("BOT") edb.stackup.add_layer("D5", "GND", layer_type="dielectric", thickness="$DIEL_T", material="ANSYS_FR4") edb.stackup.add_layer("L5", "Diel", thickness="0.05mm") edb.stackup.add_layer("D4", "GND", layer_type="dielectric", thickness="$DIEL_T", material="ANSYS_FR4") edb.stackup.add_layer("L4", "Diel", thickness="0.05mm") edb.stackup.add_layer("D3", "GND", layer_type="dielectric", thickness="$DIEL_T", material="ANSYS_FR4") edb.stackup.add_layer("L3", "Diel", thickness="0.05mm") edb.stackup.add_layer("D2", "GND", layer_type="dielectric", thickness="$DIEL_T", material="ANSYS_FR4") edb.stackup.add_layer("L2", "Diel", thickness="0.05mm") edb.stackup.add_layer("D1", "GND", layer_type="dielectric", thickness="$DIEL_T", material="ANSYS_FR4") edb.stackup.add_layer("TOP", "Diel", thickness="0.05mm") .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 62-65 Create ground planes ~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 65-89 .. code-block:: default edb.add_design_variable("PCB_W", "20mm") edb.add_design_variable("PCB_L", "20mm") gnd_dict = {} for layer_name in edb.stackup.signal_layers.keys(): gnd_dict[layer_name] = edb.modeler.create_rectangle(layer_name, "GND", [0, "PCB_W/-2"], ["PCB_L", "PCB_W/2"]) ################### # Create signal net # ~~~~~~~~~~~~~~~~~ # Create signal net on layer 3, and add clearance to the ground plane. edb.add_design_variable("SIG_L", "10mm") edb.add_design_variable("SIG_W", "0.1mm") edb.add_design_variable("SIG_C", "0.3mm") signal_path = (["5mm", 0], ["SIG_L+5mm", 0]) signal_trace = edb.modeler.create_trace(signal_path, "L3", "SIG_W", "SIG", "Flat", "Flat") signal_path = (["5mm", 0], ["PCB_L", 0]) clr = edb.modeler.create_trace(signal_path, "L3", "SIG_C*2+SIG_W", "SIG", "Flat", "Flat") gnd_dict["L3"].add_void(clr) .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 90-93 Create signal vias ~~~~~~~~~~~~~~~~~~ Create via padstack definition. Place the signal vias. .. GENERATED FROM PYTHON SOURCE LINES 93-102 .. code-block:: default edb.add_design_variable("SG_VIA_D", "1mm") edb.add_design_variable("$VIA_AP_D", "1.2mm") edb.padstacks.create("ANSYS_VIA", "0.3mm", "0.5mm", "$VIA_AP_D") edb.padstacks.place(["5mm", 0], "ANSYS_VIA", "SIG") .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 103-105 Create ground vias around signal via ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 105-111 .. code-block:: default for i in np.arange(30, 331, 30): px = np.cos(i / 180 * np.pi) py = np.sin(i / 180 * np.pi) edb.padstacks.place(["{}*{}+5mm".format("SG_VIA_D", px), "{}*{}".format("SG_VIA_D", py)], "ANSYS_VIA", "GND") .. GENERATED FROM PYTHON SOURCE LINES 112-114 Create ground vias along signal trace ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 114-119 .. code-block:: default for i in np.arange(2e-3, edb.variables["SIG_L"].value - 2e-3, 2e-3): edb.padstacks.place(["{}+5mm".format(i), "1mm"], "ANSYS_VIA", "GND") edb.padstacks.place(["{}+5mm".format(i), "-1mm"], "ANSYS_VIA", "GND") .. GENERATED FROM PYTHON SOURCE LINES 120-122 Create a wave port at the end of the signal trace ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 122-142 .. code-block:: default signal_trace.create_edge_port("port_1", "End", "Wave", horizontal_extent_factor=10) ################## # Set hfss options # ~~~~~~~~~~~~~~~~ edb.design_options.antipads_always_on = True edb.hfss.hfss_extent_info.air_box_horizontal_extent = 0.01 edb.hfss.hfss_extent_info.air_box_positive_vertical_extent = 2 edb.hfss.hfss_extent_info.air_box_negative_vertical_extent = 2 ############## # Create setup # ~~~~~~~~~~~~ setup = edb.create_hfss_setup("Setup1") setup.set_solution_single_frequency("5GHz", max_num_passes=2, max_delta_s="0.01") setup.hfss_solver_settings.order_basis = "first" .. GENERATED FROM PYTHON SOURCE LINES 143-145 Add mesh operation to setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 145-147 .. code-block:: default edb.setups["Setup1"].add_length_mesh_operation({"SIG": ["L3"]}, "m1", max_length="0.1mm") .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 148-150 Add frequency sweep to setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 150-160 .. code-block:: default setup.add_frequency_sweep( "Sweep1", frequency_sweep=[ ["linear count", "0", "1KHz", 1], ["log scale", "1KHz", "0.1GHz", 10], ["linear scale", "0.1GHz", "5GHz", "0.1GHz"], ], ) .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 161-163 Save and close EDB ~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 163-167 .. code-block:: default edb.save_edb() edb.close_edb() .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 168-170 Launch Hfss3dLayout ~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 170-173 .. code-block:: default h3d = pyaedt.Hfss3dLayout(aedb_path, specified_version=ansys_version, new_desktop_session=True) .. rst-class:: sphx-glr-script-out .. code-block:: none Initializing new desktop! .. GENERATED FROM PYTHON SOURCE LINES 174-176 Place 3D component ~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 176-188 .. code-block:: default component3d = pyaedt.downloads.download_file("component_3d", "SMA_RF_SURFACE_MOUNT.a3dcomp",) comp = h3d.modeler.place_3d_component( component_path=component3d, number_of_terminals=1, placement_layer="TOP", component_name="my_connector", pos_x="5mm", pos_y=0.000) ########## # Analysis # ~~~~~~~~ h3d.analyze(num_cores=4) .. rst-class:: sphx-glr-script-out .. code-block:: none True .. GENERATED FROM PYTHON SOURCE LINES 189-191 Create return loss plot ~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 191-193 .. code-block:: default h3d.post.create_report("dB(S(port_1, port_1))") .. rst-class:: sphx-glr-script-out .. code-block:: none .. GENERATED FROM PYTHON SOURCE LINES 194-196 Save and close the project ~~~~~~~~~~~~~~~~~~~~~~~~~~ .. GENERATED FROM PYTHON SOURCE LINES 196-199 .. code-block:: default h3d.save_project() print("Project is saved to {}".format(h3d.project_path)) h3d.release_desktop(True, True) .. rst-class:: sphx-glr-script-out .. code-block:: none Project is saved to D:/Temp/pyaedt_prj_MBU/ True .. rst-class:: sphx-glr-timing **Total running time of the script:** (3 minutes 7.263 seconds) .. _sphx_glr_download_examples_00-EDB_12_edb_sma_connector_on_board.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: 12_edb_sma_connector_on_board.py <12_edb_sma_connector_on_board.py>` .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: 12_edb_sma_connector_on_board.ipynb <12_edb_sma_connector_on_board.ipynb>` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_