EDB: Siwave analysis from EDB setup#

This example shows how you can use EDB to interact with a layout.

Perform required imports#

Perform required imports.

import shutil

import os
import time
import pyaedt

temp_folder = pyaedt.generate_unique_folder_name()
example_path = pyaedt.downloads.download_aedb(temp_folder)

targetfile = os.path.dirname(example_path)

siwave_file = os.path.join(os.path.dirname(targetfile), "Galileo.siw")
aedt_file = targetfile[:-4] + "aedt"

Launch EDB#

Launch the pyaedt.Edb class, using EDB 2022 R2 and SI units.

if os.path.exists(aedt_file):
edb = pyaedt.Edb(edbpath=targetfile, edbversion="2022.2")

Compute nets and components#

Computes nets and components. There are queries for nets, stackups, layers, components, and geometries.

print("Nets {}".format(len(edb.core_nets.nets.keys())))
start = time.time()
print("Components {}".format(len(edb.core_components.components.keys())))
print("elapsed time = ", time.time() - start)
Nets 432
Components 531
elapsed time =  0.0

Get pin position#

Get the position for a specific pin. The next section shows how to get all pins for a specific component and the positions of each of them. Each pin is a list of [X, Y] coordinate positions.

pins = edb.core_components.get_pin_from_component("U2")
for pin in pins:
[0.08144438899999999, 0.0313309]
[0.082944411, 0.0313309]
[0.08144438899999999, 0.0324739]
[0.082944411, 0.0324739]
[0.081944388, 0.0313309]
[0.082444412, 0.0313309]
[0.081944388, 0.0324739]
[0.082444412, 0.0324739]
[0.081407, 0.0319024]
[0.0829818, 0.0319024]

Get all nets connected to a component#

Get all nets connected to a specific component.

{'refdes': ['U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2', 'U2'], 'pin_name': ['1', '4', '9', '6', '2', '3', '8', '7', '10', '5'], 'net_name': ['IO0_MUX', 'IO1_GPIO', 'LVL_RXD', 'IO1', 'IO0_GPIO', 'GND', 'VSHLD_S5', 'LVL_TXD', 'IO0', 'IO1_MUX']}

Compute rats#

Computes rats.

rats = edb.core_components.get_rats()

Get all DC-connected net lists through inductance#

Get all DC-connected net lists through inductance. The inputs needed are ground net lists. The returned list contains all nets connected to a ground through an inductor.

dc_connected_net_list = edb.core_nets.get_dcconnected_net_list(GROUND_NETS)
[{'BST_V1P5_S5', 'V1P5_S5'}, {'BST_V3P3_S5', 'V3P3_S5'}, {'BST_V1P0_S0', 'V1P0_S0'}]

Get power tree based on a specific net#

Get the power tree based on a specific net.

VRM = "U3A1"
powertree_df, component_list_columns, net_group = edb.core_nets.get_powertree(OUTPUT_NET, GROUND_NETS)
for el in powertree_df:
['C4A2', '1', 'BST_V1P0_S0', 'Capacitor', '602433-057', '1']
['L4B1', '1', 'BST_V1P0_S0', 'Inductor', 'A32422-019', '1']
['U3A1', '36', 'BST_V1P0_S0', 'IC', 'G43225-001', '36-37']
['U3A1', '37', 'BST_V1P0_S0', 'IC', 'G43225-001', '36-37']
['U2A5', 'Y14', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'AB14', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'AD14', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'V14', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'Y20', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'Y18', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'Y16', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'AB20', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'AB18', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'T18', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'V20', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'V18', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['U2A5', 'V16', 'V1P0_S0', 'IC', 'IPD031-201', 'Y14-AB14-AD14-V14-Y20-Y18-Y16-AB20-AB18-T18-V20-V18-V16']
['C2L14', '1', 'V1P0_S0', 'Capacitor', 'A36096-066', '1']
['R2L19', '1', 'V1P0_S0', 'Resistor', 'E41735-001', '1']
['C3L22', '1', 'V1P0_S0', 'Capacitor', 'A36096-108', '1']
['C3B10', '1', 'V1P0_S0', 'Capacitor', '602433-081', '1']
['C2B2', '1', 'V1P0_S0', 'Capacitor', '602433-081', '1']
['C3L28', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L17', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L15', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L18', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L20', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L26', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L24', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3L29', '1', 'V1P0_S0', 'Capacitor', 'C83410-012', '1']
['C3B9', '1', 'V1P0_S0', 'Capacitor', 'C97875-001', '1']
['C3B11', '1', 'V1P0_S0', 'Capacitor', 'C97875-001', '1']
['FB3L1', '2', 'V1P0_S0', 'Other', 'G22224-001', '2']
['L4B1', '2', 'V1P0_S0', 'Inductor', 'A32422-019', '2']
['C2B12', '1', 'V1P0_S0', 'Capacitor', 'E16347-001', '1']
['C3B17', '1', 'V1P0_S0', 'Capacitor', 'E16347-001', '1']

Delete all RLCs with only one pin#

Delete all RLCs with only one pin. This method provides a useful way of removing components not needed in the simulation.

['R2B29', 'R3M13']

Delete components#

Delete manually one or more components.


Delete nets#

Delete manually one or more nets.


Get stackup limits#

Get the stackup limits (top and bottom layers and elevations).

('UNNAMED_000', 0.00203454, 'UNNAMED_012', 0.0)

Create coaxial port#

Create a coaxial port for the HFSS simulation.

edb.core_hfss.create_coax_port_on_component("U2A5", "V1P0_S0")
['U2A5_V1P0_S0_Y14', 'U2A5_V1P0_S0_AB14', 'U2A5_V1P0_S0_AD14', 'U2A5_V1P0_S0_V14', 'U2A5_V1P0_S0_Y20', 'U2A5_V1P0_S0_Y18', 'U2A5_V1P0_S0_Y16', 'U2A5_V1P0_S0_AB20', 'U2A5_V1P0_S0_AB18', 'U2A5_V1P0_S0_T18', 'U2A5_V1P0_S0_V20', 'U2A5_V1P0_S0_V18', 'U2A5_V1P0_S0_V16']

Edit stackup layers and material#

Edit the stackup layers and material. You can change stackup layer properties with assignment and create materials and assign them to layers.

edb.core_stackup.stackup_layers.layers["TOP"].thickness = "75um"
# edb.core_stackup.stackup_layers.layers["Diel1"].material_name = "Fr4_epoxy"
edb.core_stackup.create_debye_material("My_Debye", 5, 3, 0.02, 0.05, 1e5, 1e9)
# edb.core_stackup.stackup_layers.layers['BOTTOM'].material_name = "My_Debye"
# edb.core_stackup.stackup_layers.remove_layer("Signal3")
# edb.core_stackup.stackup_layers.remove_layer("Signal1")
<Ansys.Ansoft.Edb.Definition.MaterialDef object at 0x0000028BEC1B0400>

Create voltage source and Siwave DCIR analysis#

Create a voltage source and then set up a DCIR analysis.

edb.core_siwave.create_voltage_source_on_net("U2A5", "V1P5_S3", "U2A5", "GND", 3.3, 0, "V1")
edb.core_siwave.create_current_source_on_net("U1B5", "V1P5_S3", "U1B5", "GND", 1.0, 0, "I1")
setup = edb.core_siwave.add_siwave_dc_analysis("myDCIR_4")
setup.use_dc_custom_settings = True
setup.dc_slider_position = 0
setup.add_source_terminal_to_ground("V1", 1)

Save modifications#

Save modifications.

edb.core_nets.plot(None, "TOP",plot_components_on_top=True)

siw_file = edb.solve_siwave()

Export Siwave Reports#

Export all DC Reports quantities.

outputs = edb.export_siwave_dc_results(siw_file, setup.name, )
['"C:\\Program Files\\AnsysEM\\v222\\Win64\\siwave.exe"', '-embedding', '-RunScriptAndExit', '"D:\\Temp\\pyaedt_prj_D6X\\edb\\export_results.py"']

Close EDB#

Close EDB. After EDB is closed, it can be opened by AEDT.


Postprocess in Siwave#

Open Siwave and generate a report. This works on Window only.

# from pyaedt import Siwave
# siwave = Siwave("2022.2")
# siwave.open_project(siwave_file)
# report_file = os.path.join(temp_folder,'Galileo.htm')
# siwave.export_siwave_report("myDCIR_4", report_file)
# siwave.close_project()
# siwave.quit_application()

Total running time of the script: ( 1 minutes 1.709 seconds)

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